Japanese Patent Application No. 2001-221786 filed on Jul. 23, 2001, is hereby incorporated by reference in its entirety.
The present invention relates to a non-volatile semiconductor memory device including memory cells, each of the memory cells having two non-volatile memory elements and being controlled by one word gate and two control gates.
A known type of non-volatile semiconductor device is a metal-oxide-nitride-oxide semiconductor or substrate (MONOS), wherein a gate insulation layer between the channel and the gate is formed of a multi-layer stack of a silicon oxide film, a silicon nitride film, and a silicon oxide film, and charge is trapped in the silicon nitride film.
This MONOS type of non-volatile semiconductor memory device was disclosed by Y. Hayashi, et al, in 2000 Symposium on VLSI Technology Digest of Technical Papers, pp. 122-123. This document disclosed a twin MONOS flash memory cell provided with two non-volatile memory elements (MONOS memory cells) controlled by one word gate and two control gates. In other words, each flash memory cell has two charge-trapping sites. A plurality of MONOS flash memory cells of this configuration are arranged in both a row direction and a column direction, to form a memory cell array region.
Two bit lines, one word line, and two control gate lines are required for driving this MONOS flash memory cell. It should be noted, however, that these lines can be connected in common if different control gates are set to the same potential during the driving of a large number of memory cells.
In this case, a flash memory operation is data erasure, programming, or reading. Data programming and reading is usually done for selected cells for eight or 16 bits simultaneously, but data erasure is simultaneously done over a much wider range.
In such a case, data disturbance becomes a cause of concern with this type of non-volatile memory. Data disturbance refers to the disturbance of data in non-selected cells, during programming or erasure done by repeating a programming or erasure state in which a high potential is applied even to cells within the non-selected sector region by the common wiring, during programming or erasure in which a high potential is applied to the control gate line and bit line of the selected cells.
To prevent such a situation, the configuration could be such that a select gate circuit is provided to ensure that the high potential is applied only to control gates in cells in the selected sector, whereas no high potential is applied to control gates in cells in non-selected sector.
With such a configuration, however, if a voltage drop occurs in the select gates, it is necessary to supply an increased voltage to allow for that voltage drop, in order to supply a high potential to the control gates in cells in selected sectors during programming or erasure. As a result, low-voltage drive is impeded, making this unsuitable for equipment that demands a low power consumption, such as portable equipment in particular.
The present invention may provide a non-volatile semiconductor memory device enabling high-speed access when reading/writing while preventing the disturbance of data in cells in non-selected sector during programming or erasure in selected cells.
The present invention may also provide a non-volatile semiconductor memory device capable of increasing the degree of integration of memory cells while enabling high-speed access at the time of reading/writing.
The present invention may further provide a non-volatile semiconductor memory device capable of reducing power consumption.
One aspect of the present invention provides a non-volatile semiconductor memory device comprising: a memory cell array region in which are disposed a plurality of memory cells in first and second directions intersecting each other, each of the memory cells having first and second non-volatile memory elements that are controlled by one word gate and first and second control gates; and a control gate drive section which drives the first and second control gates of the memory cells within the memory cell array region.
The memory cell array region is divided in the second direction into a plurality of sector regions.
The control gate drive section has a plurality of control gate drivers each of which corresponds to one of the sector regions. Each of the control gate drivers is capable of setting a potential for the first and second control gates within the corresponding sector region, independently of other sector regions.
Each of the sector regions is divided in the first direction into a plurality of block regions, and each of the block regions has a plurality of memory cells. Each of the block regions has a plurality of sub bit lines respectively connected to the memory cells and extending in the first direction. A plurality of main bit lines are provided over the plurality of block regions extending in the first direction, and each of the main bit lines is commonly connected to the sub bit lines within the block regions. A plurality of switching elements which select connection/disconnection are provided at connections between the main bit lines and the sub bit lines.
In this aspect of the invention, each of the plurality of control gate drivers is capable of setting the potential of the first and second control gates in the corresponding sector region independently of other sector regions. Therefore, when programming the selected cells in one of the sector regions, only the control gate potential of the memory cells (selected cells and non-selected cells) in this sector region can be set to a program or erasure potential by the corresponding control gate driver. Since the potential in other sector regions can be set to a potential other than the program or erasure potential by the corresponding control gate drivers, data is not disturbed in the cells in the non-selected sector regions. This eliminates the need for select gate circuits for applying a potential only to the control gates in the specific cells in the selected block, whereby the degree of integration of the memory cells can be increased. Moreover, since a voltage drop does not occur in the select gate circuit, low voltage driving can be achieved. Therefore, the non-volatile semiconductor memory device can be effectively utilized particularly as a memory for portable equipment.
In this aspect of the invention, a plurality of switching elements which select connection/disconnection are formed at the connections between the main bit lines and the sub bit lines. Therefore, a selected sub bit line and a main bit line connected thereto can be put in a conductive state, and a non-selected sub bit line and a main bit line connected thereto can be put in a non-conductive state, by the switching elements. As a result, since the wiring capacitance of the bit lines can be decreased at the time of reading/writing, the memory cells can be accessed at a higher speed at the time of reading/writing.
In this non-volatile semiconductor memory device, each of the switching elements may be provided at an end portion of each of the sub bit lines.
In each of the block regions, an odd-numbered switching element may be connected to an end portion of an odd-numbered sub bit line on one side, and an even-numbered switching element may be connected to an end portion of an even-numbered sub bit line on the opposite side, among the plurality of the sub bit lines.
In two of the block regions adjacent to each other in the first direction, when the switching elements in one block region are referred to as first switching elements and the switching elements in the other block region are referred to as second switching elements, the first and second switching elements commonly connected to one of the main bit lines may be disposed to be adjacent to each other. If the first and second switching elements are field effect transistors which share an impurity layer, impurity layers can be shared by the first and second switching elements, whereby the degree of integration of the memory cells can be improved.